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32mx72 bits pc100 sdram registered dimm with pll, based on 32mx4 sdram with lvttl, 4 banks & 4k refresh this document is a general product description and is subject to change without notice. hynix semiconductor inc. does not assum e any responsibility for use of circuits described. no patent licenses are implied. rev. 0.4/dec. 01 2 HYM71V32D755HCT4 series description the hynix HYM71V32D755HCT4 series are 32mx72bits ecc synchronous dram modules. the modules are composed of eighteen 32mx4bits cmos synchronous drams in 400mil 54pin tsop-ii package, one 2kbit eeprom in 8pin tssop package on a 200pin glass-epoxy printed circuit board. one 0.22uf and one 0.0022uf decoupling capacitors per each sdram are mounted on the pcb. the hynix HYM71V32D755HCT4 series are dual in-line memory modules suitable for easy interchange and addition of 256mbytes memory. the hynix HYM71V32D755HCT4 series are fully synchronous operation referenced to the positive edge of the clock . all inputs and outputs are synchronized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. features ? pc100mhz support ? 200pin sdram registered dimm ? serial presence detect with eeprom ? 1.75? (44.45mm) height pcb with double sided components ? single 3.3 0.3v power supply ? all device pins are compatible with lvttl interface ? data mask function by dqm ? sdram internal banks : four banks ? module bank : one physical bank ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4 or 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ordering information part no. clock frequency internal bank ref. power sdram package plating HYM71V32D755HCT4-8 125mhz 4 banks 4k normal tsop-ii gold HYM71V32D755HCT4-p 100mhz HYM71V32D755HCT4-s 100mhz
pc100 sdram registered dimm rev. 0.4/dec. 01 3 HYM71V32D755HCT4 series pin description pin pin name description ck0 clock inputs the system clock input. all other inputs are registered to the sdram on the rising edge of clk cke0 clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh /s0 chip select enables or disables all inputs except ck, cke and dqm ba0, ba1 sdram bank address selects bank to be activated during /ras activity selects bank to be read/written during /cas activity a0 ~ a11 address row address : ra0 ~ ra11, colu mn address : ca0 ~ ca9, ca11 auto-precharge flag : a10 /ras, /cas, /we row address strobe, column address strobe, write enable /ras, /cas and /we define the operation refer function truth table for details rege register enable register enable pin which permits the dimm to operateion in buffered mode when rege input is low, in registered mode when rege input is high dqm data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq71 data input/output multiplexed data input / output pin vcc power supply (3.3v) power supply for internal circuits and input buffers v ss ground ground scl spd clock input serial presence detect clock input sda spd data input/output serial presence detect data input/output sa0~2 spd address input serial presence detect address input wp write protect for spd write protect for serial presence detect on dimm id1~3 identification detect commend interval, read precharge timing, power detect nc no connection no connection
pc100 sdram registered dimm rev. 0.4/dec. 01 4 HYM71V32D755HCT4 series pin assignments pin no. name pin no. name pin no. name pin no. name 1 vdd 51 vss 101 nc, vtt 151 ck0 2 nc, vtt 52 ras 102 nc, vtt 152 vss 3 nc, vtt 53 vss 103 vss 153 nc 4 in 54 nc 104 nc 154 s0 5 out 55 a13 105 rfu 155 vss 6 id1 56 vdd 106 rfu 156 a12 7 id2 57 a0 107 id3 157 a10 8 vss 58 a1 108 dq71 158 vdd 9 dq67 59 vss 109 dq70 159 a2 10 dq66 60 dq35 110 vss 160 a3 11 vdd 61 dq34 111 dq69 161 vss 12 dq65 62 vdd 112 dq68 162 dq31 13 dq64 63 dq33 113 vdd 163 dq30 14 vss 64 dq32 114 nc 164 vdd 15 dq63 65 vss 115 vss 165 dq29 16 dq62 66 dq27 116 nc 166 dq28 17 nc, vtt 67 dq26 117 dq59 167 vss 18 dq61 68 vss 118 dq58 168 dq23 19 dq60 69 dq25 119 vss 169 dq22 20 vdd 70 dq24 120 dq57 170 vdd 21 nc 71 vss 121 dq56 171 dq21 22 nc 72 dq19 122 vdd 172 dq20 23 vss 73 dq18 123 dq55 173 vss 24 nc 74 vdd 124 dq54 174 nc 25 nc 75 dq17 125 vss 175 nc 26 vdd 76 dq16 126 dq53 176 vdd 27 dq51 77 vss 127 dq52 177 nc 28 dq50 78 nc 128 vdd 178 vss 29 vss 79 nc, vtt 129 dq47 179 vss 30 dq49 80 vdd 130 dq46 180 nc 31 dq48 81 dq15 131 vss 181 nc 32 vdd 82 dq14 132 dq45 182 vdd 33 dq43 83 vss 133 dq44 183 dq11 34 dq42 84 dq13 134 vdd 184 dq10 35 vss 85 dq12 135 dq39 185 vss 36 dq41 86 vdd 136 dq38 186 dq9 37 dq40 87 dq7 137 vss 187 dq8 38 vdd 88 dq6 138 dq37 188 vdd 39 a4 89 vss 139 dq36 189 dq3 40 a5 90 dq5 140 vdd 190 dq2 41 gnd 91 dq4 141 a6 191 vss 42 a8 92 vdd 142 a7 192 dq1 43 a9 93 pde# 143 vss 193 dq0 44 vdd 94 pd1 144 a11 194 sda 45 nc 95 pd2 145 nc 195 sa0 46 cke0 96 pd3 146 vdd 196 sa1 47 vss 97 pd4 147 dqm 197 sa2 48 cas 98 scl 148 we 198 vdd 49 nc, vtt 99 nc 149 vss 199 nc, vtt 50 vdd 100 vss 150 nc 200 nc, vtt
pc100 sdram registered dimm rev. 0.4/dec. 01 5 HYM71V32D755HCT4 series block diagram dq0 dq1 dq2 dq3 u0 u1 u2 u3 dqm cs dqm cs dqm cs dqm cs rdqm dqm cs u4 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq64 dq65 dq66 dq67 dq0 dq1 dq2 dq3 dq0 dq1 dq2 dq3 dq0 dq1 dq2 dq3 dq0 dq1 dq2 dq3 dq0 dq1 dq2 dq3 rs0 u9 u10 u11 u12 dqm cs dqm cs dqm cs dqm cs dqm cs u13 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq68 dq69 dq70 dq71 dq0 dq1 dq2 dq3 dq0 dq1 dq2 dq3 dq0 dq1 dq2 dq3 dq0 dq1 dq2 dq3 dq0 dq1 dq2 dq3 u5 u6 u7 u8 dqm cs dqm cs dqm cs dqm cs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq0 dq1 dq2 dq3 dq0 dq1 dq2 dq3 dq0 dq1 dq2 dq3 dq0 dq1 dq2 dq3 u14 u15 u16 u17 dqm cs dqm cs dqm cs dqm cs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dq0 dq1 dq2 dq3 dq0 dq1 dq2 dq3 dq0 dq1 dq2 dq3 dq0 dq1 dq2 dq3 v cc v ss bypass capacitor two 0.0022uf and one 0.22uf per sdram a0 a1 a2 sa2 serial pd sda scl wp sa0 sa1 u0 ~ u35 u0 ~ u35 s0 ba0,ba1 r e g i s t e r a0 ~ a11 ras dqm cas cke0 we rs0 u0~17 rdqm u0~17 u0~17 u0~17 u0~17 u0~17 rege pll clk * when necessary two couples of the signals are created by double loading the register inputs. +3.3v 3.3v id1=command, interval 0=2clocks 1=1clocks id2=read precharge timing 0=no early ras 1=early ras id3=power detect 0=normal 1=low power ck0 pll id1 id2 id3
pc100 sdram registered dimm rev. 0.4/dec. 01 6 HYM71V32D755HCT4 series serial presence detect byte number function description function value note -8 -p -s -8 -p -s byte0 # of bytes written into serial memory at module manufacturer 128 bytes 80h byte1 total # of bytes of spd memory device 256 bytes 08h byte2 fundamental memory type sdram 04h byte3 # of row addresses on this assembly 12 0ch 1 byte4 # of column addresses on this assembly 11 0bh byte5 # of module banks on this assembly 1 bank 01h byte6 data width of this assembly 72 bits 48h byte7 data width of this assembly (continued) - 00h byte8 voltage interface standard of this assembly lvttl 01h byte9 sdram cycle time @/cas latency=3 8ns 10ns 10ns 80h a0h a0h byte10 access time from clock @/cas latency=3 6ns 6ns 6ns 60h 60h 60h byte11 dimm configuration type ecc 02h byte12 refresh rate/type 15.625us / self refresh supported 80h byte13 primary sdram width x4 04h byte14 error checking sdram width x4 04h byte15 minimum clock delay back to back random column address tccd = 1 clk 01h byte16 burst lenth supported 1,2,4,8,full page 8fh 2 byte17 # of banks on each sdram device 4 banks 04h byte18 sdram device attributes, /cas lataency /cas latency=2,3 06h byte19 sdram device attributes, /cs lataency /cs latency=0 01h byte20 sdram device attributes, /we lataency /we latency=0 01h byte21 sdram module attributes registered inputs, with pll 16h byte22 sdram device attributes, general +/- 10% voltage tolerence, burst read single bit write, precharge all, auto precharge, early ras precharge 0eh byte23 sdram cycle time @/cas latency=2 8ns 10ns 12ns a0h a0h c0h byte24 access time from clock @/cas latency=2 6ns 6ns 6ns 60h 60h 60h byte25 sdram cycle time @/cas latency=1 - - - 00h 00h 00h byte26 access time from clock @/cas latency=1 - - - 00h 00h 00h byte27 minimum row precharge time (trp) 20ns 20ns 20ns 14h 14h 14h byte28 minimum row active to row active delay (trrd) 16ns 20ns 20ns 10h 14h 14h byte29 minimum /ras to /cas delay (trcd) 20ns 20ns 20ns 14h 14h 14h byte30 minimum /ras pulse width (tras) 48ns 50ns 50ns 30h 32h 32h byte31 module bank density 256mb 40h byte32 command and address signal input setup time 2ns 2ns 2ns 20h 20h 20h byte33 command and address signal input hold time 1ns 1ns 1ns 10h 10h 10h byte34 data signal input setup time 2ns 2ns 2ns 20h 20h 20h byte35 data signal input hold time 1ns 1ns 1ns 10h 10h 10h byte36 ~61 superset information (may be used in future) - 00h byte62 spd revision intel spd 1.2b 12h 3, 8 byte63 checksum for byte 0~62 - 31h 57h 77h byte64 manufacturer jedec id code hynix jeded id adh byte65 ~71 ....manufacturer jedec id code unused ffh byte72 manufacturing location hsi(korea area) hsa (united states area) hse (europe area) hsj (japan area) hss(singapore) asia area 0*h 1*h 2*h 3*h 4*h 5*h 9
pc100 sdram registered dimm rev. 0.4/dec. 01 7 HYM71V32D755HCT4 series byte number function description function value note -8 -p -s -8 -p -s byte73 manufacturer?s part number (component) 7 (sdram) 37h 4, 5 byte74 manufacturer?s part number (128mb based) 131h4, 5 byte75 manufacturer?s part number (voltage interface) v (3.3v, lvttl) 56h 4, 5 byte76 manufacturer?s part number (memory width) 333h4, 5 byte77 ....manufacturer?s part number (memory width) 232h4, 5 byte78 manufacturer?s part number (module type) d44h4, 5 byte79 manufacturer?s part number (data width) 737h4, 5 byte80 ....manufacturer?s part number (data width) 535h4, 5 byte81 manufacturer?s part number (refresh, sdram bank) 5 (4k refresh, 4banks) 35h 4, 5 byte82 manufacturer?s part number (generation) h48h4, 5 byte83 manufacturer?s part number (generation) c43h4, 5 byte84 manufacturer?s part number (package type) t54h4, 5 byte85 manufacturer?s part number (component configuration) 4 (x4 based) 34h 4, 5 byte86 manufacturer?s part number (hyphent) - (hyphen) 2dh 4, 5 byte87 manufacturer?s part number (min. cycle time) 8 p s 38h 50h 53h 4, 5 byte88 ~90 manufacturer?s part number blanks 20h 4, 5 byte91 revision code (for component) process code - 4, 6 byte92 ....revision code (for pcb) process code - 4, 6 byte93 manufacturing date ye ar - 3, 6 byte94 ....manufacturing date work week - 3, 6 byte95 ~98 assembly serial number serial number - 6 byte99 ~125 manufacturer specific data (may be used in future) none 00h byte126 system frequency support 100mhz 64h 7, 8 byte127 intel specification details for 100mhz support refer to note7 8fh 8fh 8dh 7, 8 byte128 ~256 unused storage locations -00h continued note : 1. the bank address is excluded 2. 1, 2, 4, 8 for interleave burst type 3. bcd adopted 4. ascii adopted 5. basically hynix writes part no. except for ?hym? in byte 73~90 to use the limited 18 bytes from byte 73 to byte 90 6. not fixed but dependent 7. ck0 connected to dimm, tbd junction temp, cl2(3) support, intel defined concurrent auto precharge support 8. refer to intel spd specification 1.2b 9. refer to hsi web site.
pc100 sdram registered dimm rev. 0.4/dec. 01 8 HYM71V32D755HCT4 series absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability. dc operating condition (t a =0 to 70 c ) note : 1.all voltages are referenced to v ss = 0v 2.v ih (max) is acceptable 5.6v ac pulse width with <=3ns of duration. 3.v il (min) is acceptable -2.0v ac pulse width with <=3ns of duration. ac operating test condition (t a =0 to 70 c , v dd =3.3 0.3v, v ss =0v) note : 1.output load to measure access times is equivalent to two ttl gates and one capacitor (50pf). for details, refer to ac/dc outp ut load circuit parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 18 w soldering temperature ? time t solder 260 ? 10 c ? sec parameter symbol min typ max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq + 0.3 v 1,2 input low voltage v il -0.3 0 0.8 v 1,3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voltage voutref 1.4 v output load capacitance for access time measurement c l 50 pf 1
pc100 sdram registered dimm rev. 0.4/dec. 01 9 HYM71V32D755HCT4 series capacitance (ta=25 c , f=1mhz) output load circuit parameter pin symbol -8/p/s unit min max input capacitance ck0 c i1 -44pf cke0 c i2 -20pf /s0, /s2 c i3 -20pf a0~11, ba0, ba1 c i4 -20pf /ras, /cas, /we c i5 -20pf dqm0~dqm7 ci 6 -20pf data input / output capacitance dq0 ~ dq63 c i/o -20pf vtt=1.4v rt=250 ? 50pf output 50pf output dc output load circuit ac output load circuit
pc100 sdram registered dimm rev. 0.4/dec. 01 10 HYM71V32D755HCT4 series dc characteristics i (ta=0 to 70 c , v dd =3.3 0.3v) note : 1.v in = 0 to 3.6v, all other pins are not tested under v in =0v 2.d out is disabled, v out =0 to 3.6 dc characteristics ii note : 1. i dd1 and i dd4 depend on output loading and cycle rates. specified values are measured with the output open 2. min. of trrc (refresh ras cycle time) is shown at ac characteristics ii parameter symbol min. max unit note input leakage current i li -10 10 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -2ma output low voltage v ol -0.4vi ol = +2ma parameter symbol test condition speed unit note -8 -p -s operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 2500 2200 2200 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = 15ns 356 ma i dd2ps cke v il (max), t ck = 178 precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 30ns. all other pins v dd -0.2v or 0.2v 570 ma i dd2ns cke v ih (min), t ck = input signals are stable. 570 active standby current in power down mode i dd3p cke v il (max), t ck = 15ns 320 ma i dd3ps cke v il (max), t ck = 155 active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 30ns. all other pins v dd -0.2v or 0.2v 840 ma i dd3ns cke v ih (min), t ck = input signals are stable. 400 burst mode operating current i dd4 t ck t ck (min), i ol =0ma all banks active cl=3 2900 2700 2700 ma 1 cl=2 3200 2700 2700 auto refresh current i dd5 t rrc t rrc (min), all banks active 4800 ma 2 self refresh current i dd6 cke 0.2v 276 ma
pc100 sdram registered dimm rev. 0.4/dec. 01 11 HYM71V32D755HCT4 series aac characteristics i (ac operating conditions unless otherwise noted) note : 1. in registered dimm, data is delayed an additional clock cycle due to the register (this is, device cl + 1 = dimm cl) 2.assume tr / tf (input rise and fall time ) is 1ns, if tr & tf > 1ns, then [(tr+tf)/2-1]ns should be added to the parameter 3.access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v if tr > 1ns, then (tr/2-0. 5)ns should be added to the parameter parameter symbol -8 -p -s unit note min max min max min max system clock cycle time cas latency = 3 tck3 8 1000 10 1000 10 1000 ns 1 cas latency = 2 tck2 10 10 12 clock high pulse width tchw 3 - 3 - 3 - ns 2 clock low pulse width tclw 3 - 3 - 3 - ns 2 access time from clock cas latency = 3 tac3 - 6 - 6 - 6 ns 3 cas latency = 2 tac2 - 6 - 6 - 6 ns data-out hold time toh 3 - 3 - 3 - ns data-input setup time tds 2 - 2 - 2 - ns 2 data-input hold time tdh 1 - 1 - 1 - ns 2 address setup time tas 2 - 2 - 2 - ns 2 address hold time tah 1 - 1 - 1 - ns 2 cke setup time tcks 2 - 2 - 2 - ns 2 cke hold time tckh 1 - 1 - 1 - ns 2 command setup time tcs 2 - 2 - 2 - ns 2 command hold time tch 1 - 1 - 1 - ns 2 clk to data output in low-z time tolz 1 - 1 - 1 - ns clk to data output in high-z time cas latency = 3tohz3 3 63636ns cas latency = 2tohz2 3 63636ns
pc100 sdram registered dimm rev. 0.4/dec. 01 12 HYM71V32D755HCT4 series ac characteristics ii note : 1. timing delay due to the register is considered in a registered dimm 2. a new command can be given trrc after self refresh exit parameter symbol -8 -p -s unit note min max min max min max ras cycle time operation trc 68 - 70 - 70 - ns auto refresh trrc 68 - 70 - 70 - ns ras to cas delay trcd 20 - 20 - 20 - ns ras active time tras 48 100k 50 100k 50 100k ns ras precharge time trp 20 - 20 - 20 - ns ras to ras bank active delay trrd 16 - 20 - 20 - ns cas to cas delay tccd 1 - 1 - 1 - clk write command to data-in delay twtl 1 - 1 - 1 - clk 1 data-in to precharge command tdpl 0 - 0 - 0 - clk 1 data-in to active command tdal 3 - 2 - 2 - clk 1 dqm to data-out hi-z tdqz 3 - 3 - 3 - clk 1 dqm to data-in mask tdqm 0 - 0 - 0 - clk mrs to new command tmrd 2 - 2 - 2 - clk precharge to data output hi-z cas latency = 3 tproz3 4 - 4 - 4 - clk 1 cas latency = 2 tproz2 3 - 3 - 3 - power down exit time tpde 1 - 1 - 1 - clk self refresh exit time tsre 1 - 1 - 1 - clk 2 refresh time tref - 64 - 64 - 64 ms
pc100 sdram registered dimm rev. 0.4/dec. 01 13 HYM71V32D755HCT4 series device operating option table HYM71V32D755HCT4-8 HYM71V32D755HCT4-p HYM71V32D755HCT4-s note : dimm/cas latency = device cl + 1 (registered mode) cas latency trcd tras trc trp tac toh 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 3clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns
pc100 sdram registered dimm rev. 0.4/dec. 01 14 HYM71V32D755HCT4 series command truth table note : 1. exiting self refresh occurs by asyn chronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank addr ess, ra = row address, ca = column address, opcode = operand code, nop = no operation 3. the burst read sigle write mode is ent ered by programming the write burst mode bit (a9) in the mode register to a logic 1. command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x llllx op code no operation h x hxxx xx lhhh bank active h x l l h h x ra v read hxlhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single-write h x llllx a9 pin high (other pins op code) mrs mode self refresh 1 entry h l lllhx x exit l h hxxx x lhhh precharge power down entry h l hxxx x x lhhh exit l h hxxx x lhhh clock suspend entry h l hxxx x x lvvv exit l h x x
pc100 sdram registered dimm rev. 0.4/dec. 01 15 HYM71V32D755HCT4 series package demension notes : 1. all dimensions are in milimeters 2. tolerances on all dimmensions 0.127 unless otherwise. 153.67 147.67 83.82 10.00 44.45 "a" detail ? a" unit: mm 28.12 r 2.0 r 3.0 x 2 50(1.27) 157.48(4.0) min. 4.00 max. 0.99 0.05 2.0 0.1 3.12 r 1.00 0.10 2.79

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